- Written by Deepak Sebastian
- Posted on August 31, 2023
- Updated on October 9, 2024
- 5373 Views
Agile ports allow users to connect 40G interfaces on 7130 products utilizing multiple SFP ports per 40G capable interface. This enables 40G capable applications, such as MetaConnect and MetaWatch, to operate at that speed.
- Written by David Joseph
- Posted on August 31, 2023
- Updated on October 9, 2024
- 4699 Views
Arista’s DCS-7130B series of switches are network devices designed for ultra low-latency applications along with a suite of networking features.
- Written by David Joseph
- Posted on December 24, 2024
- Updated on December 24, 2024
- 17 Views
This feature adds support for the front panel Ethernet (Et) interface counters on the platforms listed below and enables the Et interfaces to dynamically adopt the counter values (packet and error)1 of interfaces (Switch, App interfaces etc.) related to the currently running FPGA application, based on user or default configuration. All Arista FPGA applications are supported. Both the receive and transmit packet counters can be independently configured for each interface, as desired. Counters are supported for interfaces of any speed including agile ports.
- Written by Paul Fallon
- Posted on March 17, 2021
- Updated on March 17, 2021
- 6813 Views
For an octal port such as a QSFPDD or OSFP, this feature renumbers the ports on a system to have 4 configurable
- Written by Manpreet
- Posted on March 3, 2023
- Updated on May 22, 2023
- 5385 Views
The on boot link override feature adds support for keeping interfaces down at switch boot until the correct interface state can be determined by feature agents. Keeping the interfaces down through device boot will protect against transient traffic loss by preventing downstream peers from detecting a transient interface up and sending traffic to the device.
- Written by Shreyas Ruwala
- Posted on June 9, 2021
- Updated on February 5, 2022
- 7388 Views
Interfaces will transition into an error disabled state due to reasons like excessive link flaps or speed mismatch. A